This invention relates to a method of improving adhesion between a semiconductor substrate and a dielectric layer. The method relates also to a structure comprising a semiconductor substrate, a dielectric layer and a silicon dioxide adhesion layer.
There are a great many processes, structures and devices of commercial significance which involve the deposition of a dielectric layer onto a surface of a semiconductor substrate. One example is the manufacture of CIS (CMOS Image Sensor) products. In these manufacturing processes, it is necessary to deposit a dielectric layer by plasma enhanced chemical vapour deposition (PECVD) for TSV (Through Silicon Via) isolation and interposer passivation in via reveal applications. Low temperature, high etch rate silicon etch processes produce a significant amount of unwanted polymeric by-product. This is particularly pronounced in TSV and Via Reveal Applications. The polymer by-product needs to be removed before any isolation layers are deposited. One reason for this is that the presence of polymeric by-product compromises the adhesion of subsequently deposited dielectric layers. Removal of the by-product requires multiple cleaning steps, including O2 ashing and an EKC polymer strip. These processes can themselves result in other residues remaining on the silicon surface. These residues can also result in poor adhesion of dielectric layers.
Typically, 300 mm silicon substrates are bonded to glass carrier substrates prior to thinning and etching of the silicon. The adhesive used for the bonding has unstable vacuum properties which necessitate that outgassing is carried out prior to CVD deposition. However, there is potential for the outgas by-products to contaminate the silicon surface. Contamination of the silicon surface by processes such as these is undesirable. One consequence of the contamination is that the adhesion of subsequently deposited dielectric layers is compromised. Therefore, it can be seen that it can be challenging to ensure adequate adhesion of dielectric layers to semiconductor structures as part of commercial fabrication processes.